A Fine-Grain Local Clock Generator Architecture to Enable Dynamic Frequency Scaling in MPSoCs

Synchronous MPSoCs are widespread today, but the evolution of technology into the deep submicron domain leads to increasingly complex timing closure problems. One natural solution to these is to resort to the globally asynchronous, locally synchronous (GALS) paradigm. This work proposes a novel architecture for clock generators to support GALS systems. The generator can drive individual modules of an MPSoC, e.g. NoC routers and processing modules. The main design objectives were low power and area overheads. This generator produces 16 distinct operating frequencies between 90 MHz and 1 GHz. It supports clock gating, glitchfree frequency switching and is robust to PVT variations.